[all-commits] [llvm/llvm-project] 447750: [RISCV] ISel (and (shift X, C1), C2)) to shift pai...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4477500533281c90c6ce70eb87271f61fd6a415f
      https://github.com/llvm/llvm-project/commit/4477500533281c90c6ce70eb87271f61fd6a415f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-30 (Wed, 30 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/bitreverse-shift.ll
    M llvm/test/CodeGen/RISCV/bswap-shift.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases

Previously, these isel optimizations were disabled if the AND could
be selected as a ANDI instruction. This patch disables the optimizations
only if the immediate is valid for C.ANDI. If we can't use C.ANDI,
we might be able to compress the shift instructions instead.

I'm not checking the C extension since we have relatively poor test
coverage of the C extension. Without C extension the code size
should be equal. My only concern would be if the shift+andi had
better latency/throughput on a particular CPU.

I did have to add a peephole to match SRLIW if the input is zexti32
to prevent a regression in rv64zbp.ll.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D122701