[all-commits] [llvm/llvm-project] e18cc5: [SDAG] try to canonicalize logical shift after bswap

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e18cc5277fd8f29da6ba5273a2f4c8359754ccb6
      https://github.com/llvm/llvm-project/commit/e18cc5277fd8f29da6ba5273a2f4c8359754ccb6
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-03-30 (Wed, 30 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/arm64-rev.ll
    M llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
    M llvm/test/CodeGen/AArch64/load-combine.ll
    M llvm/test/CodeGen/ARM/load-combine-big-endian.ll
    M llvm/test/CodeGen/ARM/load-combine.ll
    M llvm/test/CodeGen/RISCV/bswap-shift.ll
    M llvm/test/CodeGen/X86/combine-bswap.ll

  Log Message:
  -----------
  [SDAG] try to canonicalize logical shift after bswap

When shifting by a byte-multiple:
bswap (shl X, C) --> lshr (bswap X), C
bswap (lshr X, C) --> shl (bswap X), C

This is the backend version of D122010 and an alternative
suggested in D120648.
There's an extra check to make sure the shift amount is
valid that was not in the rough draft.

I'm not sure if there is a larger motivating case for RISCV (bug report?),
but the ARM diffs show a benefit from having a late version of the
transform (because we do not combine the loads in IR).

Differential Revision: https://reviews.llvm.org/D122655