[all-commits] [llvm/llvm-project] 4cb85d: [RISCV] Add CMIX isel pattern for (xor (and (xor r...

[LiqinWeng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4cb85da811243d0a32a909c9e06f18fadd7b76fe
      https://github.com/llvm/llvm-project/commit/4cb85da811243d0a32a909c9e06f18fadd7b76fe
  Author: Liqin Weng <Liqin.Weng at streamcomputing.com>
  Date:   2022-03-30 (Wed, 30 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv32zbt.ll
    M llvm/test/CodeGen/RISCV/rv64zbt.ll

  Log Message:
  -----------
  [RISCV] Add CMIX isel pattern for (xor (and (xor rs1, rs3), rs2), rs3)

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D122702