[all-commits] [llvm/llvm-project] 750475: [RISCV] Trim RVV isel pats matchable via DAG post-...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 75047577d6518bad5be84ec75ece8f8425148d33
      https://github.com/llvm/llvm-project/commit/75047577d6518bad5be84ec75ece8f8425148d33
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2022-03-30 (Wed, 30 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Trim RVV isel pats matchable via DAG post-process

In D122512, several masked patterns were added to support lowering of
vector-predicated float-to-int and int-to-float conversions. With the
introduction of these patterns, all of the old "unmasked" patterns are
matchable via the DAG post-process introduced in D118810, once the relevant
opcode entries are set up in the helper table.

Locally this reduces the generated isel table by 4%.

Reviewed By: arcbbb

Differential Revision: https://reviews.llvm.org/D122637