[all-commits] [llvm/llvm-project] e68257: [RISCV][SelectionDAG] Enable TargetLowering::hasBi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e68257fceee7e811d0c554f164705da2959c7519
      https://github.com/llvm/llvm-project/commit/e68257fceee7e811d0c554f164705da2959c7519
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-28 (Mon, 28 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    A llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll

  Log Message:
  -----------
  [RISCV][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI.

Modified DAGCombiner to pass the shift the bittest input and the shift amount
to hasBitTest. This matches the other call to hasBitTest in TargetLowering.h

This is an alternative to D122454.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D122458