[all-commits] [llvm/llvm-project] cac977: [SelectionDAG] Don't create entries in ValueMap in...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cac9773dccd95cd442d2852b7ced0a8a311504f6
      https://github.com/llvm/llvm-project/commit/cac9773dccd95cd442d2852b7ced0a8a311504f6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-23 (Wed, 23 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

  Log Message:
  -----------
  [SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo

Instead of using operator[], use DenseMap::find to prevent default
constructing an entry if it isn't already in the map.

Also simplify a condition to check for 0 instead of a virtual register.
I'm pretty sure we can only get 0 or a virtual register out of the value
map.