[all-commits] [llvm/llvm-project] 51940d: [RISCV] Special case sign extended scalars when ty...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51940d69cb5d95417b914ec75961ffb78901fb53
      https://github.com/llvm/llvm-project/commit/51940d69cb5d95417b914ec75961ffb78901fb53
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-22 (Tue, 22 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vadd.ll

  Log Message:
  -----------
  [RISCV] Special case sign extended scalars when type legalizing nxvXi64 .vx instrinsics on RV32.

On RV32, we need to type legalize i64 scalar arguments to intrinsics.
We usually do this by splatting the value into a vector separately.
If the scalar happens to be sign extended, we can continue using a .vx
intrinsic.

We already special cased sign extended constants, this extends it
to any sign extended value.

I've only added tests for one case of vadd. Most intrinsics go
through the same check.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D122186