[all-commits] [llvm/llvm-project] 10fd28: [RISCV] Add policy operand for masked compare and ...

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 10fd2822b77e12215b4ea82fc6d0a052961eb9d9
      https://github.com/llvm/llvm-project/commit/10fd2822b77e12215b4ea82fc6d0a052961eb9d9
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2022-03-22 (Tue, 22 Mar 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsif.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsof.ll

  Log Message:
  -----------
  [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR
intrinsics.

Those operations are updated under a tail agnostic policy, but they
could have mask agnostic or undisturbed.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D120228