[all-commits] [llvm/llvm-project] abb5a9: [RISCV] Support mask policy for RVV IR intrinsics.

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: abb5a985e96acda93901fabf0f5be5b8a4422374
      https://github.com/llvm/llvm-project/commit/abb5a985e96acda93901fabf0f5be5b8a4422374
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2022-03-22 (Tue, 22 Mar 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInstrFormats.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    A llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    A llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
    A llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
    A llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
    R llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll

  Log Message:
  -----------
  [RISCV] Support mask policy for RVV IR intrinsics.

Add the UsesMaskPolicy flag to indicate the operations result
would be effected by the mask policy. (ex. mask operations).

It means RISCVInsertVSETVLI should decide the mask policy according
by mask policy operand or passthru operand.
If UsesMaskPolicy is false (ex. unmasked, store, and reduction operations),
the mask policy could be either mask undisturbed or agnostic.
Currently, RISCVInsertVSETVLI sets UsesMaskPolicy operations default to
MA, otherwise to MU to keep the current mask policy would not be changed
for unmasked operations.

Add masked-tama, masked-tamu, masked-tuma and masked-tumu test cases.
I didn't add all operations because most of implementations are using
the same pseudo multiclass. Some tests maybe be duplicated in different
tests. (ex. masked vmacc with tumu shows in vmacc-rv32.ll and masked-tumu)
I think having different tests only for policy would make the testing
clear.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D120226