[all-commits] [llvm/llvm-project] dd3b90: [AArch64] Combine ISD::SETCC into AArch64ISD::ANDS

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dd3b90e4d77b0cc874ffcaaeb28776ba0fd15032
      https://github.com/llvm/llvm-project/commit/dd3b90e4d77b0cc874ffcaaeb28776ba0fd15032
  Author: chenglin.bi <chenglin.bi at cixcomputing.com>
  Date:   2022-03-19 (Sat, 19 Mar 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-xaluo.ll

  Log Message:
  -----------
  [AArch64] Combine ISD::SETCC into AArch64ISD::ANDS

When N > 12, (2^N -1) is not a legal add immediate (isLegalAddImmediate will return false).
ANd if SetCC input use this number, DAG combiner will generate one more SRL instruction.
So combine [setcc (srl x, imm), 0, ne] to [setcc (and x, (-1 << imm)), 0, ne] to get better optimization in emitComparison
Fix https://github.com/llvm/llvm-project/issues/54283

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D121449