[all-commits] [llvm/llvm-project] 7afa44: [RISCV] Add more sign-extending ops to MIR sext.w ...

[mohammed-nurulhoque via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7afa44f5f57e6f3ccf8717a76073126d489c0ef8
      https://github.com/llvm/llvm-project/commit/7afa44f5f57e6f3ccf8717a76073126d489c0ef8
  Author: Mohammed Nurul Hoque <mohammed.nurulhoque at imgtec.com>
  Date:   2022-03-18 (Fri, 18 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
    M llvm/test/CodeGen/RISCV/sextw-removal.ll

  Log Message:
  -----------
  [RISCV] Add more sign-extending ops to MIR sext.w pass.

This patch adds single-bit and bit-counting ops to list of sign-extending ops.

A single-bit write propagates sign-extendedness if it's not in the sign-bits.

Bit extraction and bit counting always outputs a small number, so sign-extended.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121152