[all-commits] [llvm/llvm-project] f49633: [ARM] Fix Decode of tsb csync

[Sam Elliott via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f496330f9719ddce4b9e769c7fa49d0fcad643b8
      https://github.com/llvm/llvm-project/commit/f496330f9719ddce4b9e769c7fa49d0fcad643b8
  Author: Archibald Elliott <archibald.elliott at arm.com>
  Date:   2022-03-17 (Thu, 17 Mar 2022)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/ARM/ARMInstrThumb2.td
    M llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    M llvm/test/MC/ARM/armv8.4a-trace.s

  Log Message:
  -----------
  [ARM] Fix Decode of tsb csync

There is a crash in the ARM backend when attempting to decode a "tsb
csync" instruction using `llvm-objdump --triple=armv8.4a -d`. The crash
was in `ARMMCInstrAnalysis::evaluateBranch` where the number of operands
in the decoded instruction (0) did not match the number of operands in
the instruction description (1).

This is becuase `tsb csync` looks like it has an operand during
assembly, but there is only one valid operand (csync), so there is no
encoding space in the instruction for the operand, so the decoder never
has a field to decode that represents `csync`.

The fix is to add a custom decode method, which ensures that this
instruction does have the right number of operands after decoding. This
method merely adds the only available operand value, `ARM_TSB::CSYNC`.

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D121479