[all-commits] [llvm/llvm-project] bbd2ec: [RISCV] Add +experimental-zvfh extension to cover ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bbd2ecf9f095035a91a777fc1ec2fcfbc114e3c0
      https://github.com/llvm/llvm-project/commit/bbd2ecf9f095035a91a777fc1ec2fcfbc114e3c0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-17 (Thu, 17 Mar 2022)

  Changed paths:
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlsegff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnot.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vcompress.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfabs.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfneg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnot.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vreinterpret.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg_mask.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vssseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg_mask.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vundefined.c
    M clang/utils/TableGen/RISCVVEmitter.cpp
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/Analysis/CostModel/RISCV/fixed-vector-gather.ll
    M llvm/test/Analysis/CostModel/RISCV/fixed-vector-scatter.ll
    M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
    M llvm/test/Analysis/CostModel/RISCV/splice.ll
    M llvm/test/CodeGen/RISCV/rvv/cmp-folds.ll
    M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
    M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/select-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/splat-vectors.ll
    M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
    M llvm/test/CodeGen/RISCV/rvv/undef-vp-ops.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.f.s.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrec7.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmax.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredmin.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsqrt7.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfrsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnj.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjn.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsgnjx.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1down.ll
    M llvm/test/CodeGen/RISCV/rvv/vfslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll
    M llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfeq.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfge.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfgt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfle.ll
    M llvm/test/CodeGen/RISCV/rvv/vmflt.ll
    M llvm/test/CodeGen/RISCV/rvv/vmfne.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpload.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vse-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsse-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsse-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

  Log Message:
  -----------
  [RISCV] Add +experimental-zvfh extension to cover half types in vectors.

Currently we allow half types in vectors if the scalar Zfh extension
is enabled. This behavior is not inline with the vector spec. For f32
and f64 types, the Zve32f, Zve64f, Zve64d, and V explicitly control
the availablity of floating point types in vectors.

In order to make our compiler compliant, we either need to remove all support
for half in vectors or we need an extension to control it.

Draft spec here https://github.com/riscv/riscv-v-spec/pull/780

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D121345