[all-commits] [llvm/llvm-project] 0b6df4: [AArch64] Combine ISD::AND into AArch64ISD::ANDS

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0b6df40c52acf8a1af7ad370a12521879e8ef96a
      https://github.com/llvm/llvm-project/commit/0b6df40c52acf8a1af7ad370a12521879e8ef96a
  Author: David Green <david.green at arm.com>
  Date:   2022-03-17 (Thu, 17 Mar 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/peephole-and-tst.ll

  Log Message:
  -----------
  [AArch64] Combine ISD::AND into AArch64ISD::ANDS

If we already have a AArch64ISD::ANDS node with identical operands, we
can merge any ISD::AND into it, reducing the instruction count by
calculating the value and the flags in a single operation. This code is
taken from the X86 backend, and could also handle AArch64ISD::ADDS and
AArch64ISD::SUBS, but I couldn't find any test cases where it came up.

Differential Revision: https://reviews.llvm.org/D118584