[all-commits] [llvm/llvm-project] 37b378: [NFC][CodeGen] Rename some functions in MachineIns...

[KanRobert via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 37b378386eefab39ef570db6172a8b8e660d7bfb
      https://github.com/llvm/llvm-project/commit/37b378386eefab39ef570db6172a8b8e660d7bfb
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2022-03-16 (Wed, 16 Mar 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineInstr.h
    M llvm/lib/CodeGen/EarlyIfConversion.cpp
    M llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/LiveRangeEdit.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/MachineInstr.cpp
    M llvm/lib/CodeGen/MachineLoopUtils.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/ModuloSchedule.cpp
    M llvm/lib/CodeGen/PeepholeOptimizer.cpp
    M llvm/lib/CodeGen/ProcessImplicitDefs.cpp
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/lib/CodeGen/TailDuplicator.cpp
    M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
    M llvm/lib/CodeGen/UnreachableBlockElim.cpp
    M llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
    M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
    M llvm/lib/Target/ARC/ARCOptAddrMode.cpp
    M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
    M llvm/lib/Target/ARM/ARMSLSHardening.cpp
    M llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
    M llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
    M llvm/lib/Target/AVR/AVRRegisterInfo.cpp
    M llvm/lib/Target/CSKY/CSKYRegisterInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
    M llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
    M llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
    M llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
    M llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
    M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
    M llvm/lib/Target/Hexagon/HexagonPeephole.cpp
    M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
    M llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
    M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
    M llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.cpp
    M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
    M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
    M llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
    M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
    M llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/lib/Target/X86/X86ExpandPseudo.cpp
    M llvm/lib/Target/X86/X86FloatingPoint.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstructionSelector.cpp
    M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp

  Log Message:
  -----------
  [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments