[all-commits] [llvm/llvm-project] 6a5477: [RISCV] Select SRLI+SLLI for AND with leading ones...

[Haocong Lu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a54776fe0092c251ee3783c0c25d14699467896
      https://github.com/llvm/llvm-project/commit/6a54776fe0092c251ee3783c0c25d14699467896
  Author: Haocong.Lu <Haocong.Lu at streamcomputing.com>
  Date:   2022-03-16 (Wed, 16 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/and.ll
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/double-arith.ll
    M llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
    M llvm/test/CodeGen/RISCV/double-intrinsics.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll

  Log Message:
  -----------
  [RISCV] Select SRLI+SLLI for AND with leading ones mask

Select SRLI+SLLI for and i64 %x, imm if the imm is a leading ones mask.
It's useful in RV64 when the mask exceeds simm32 (cannot be generated by LUI).

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121598