[all-commits] [llvm/llvm-project] 356833: [AArch64] Perform last active true vector combine

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3568333815b30dc565ce041c64e871bc1d4e8e21
      https://github.com/llvm/llvm-project/commit/3568333815b30dc565ce041c64e871bc1d4e8e21
  Author: zhongyunde <zhongyunde at huawei.com>
  Date:   2022-03-15 (Tue, 15 Mar 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll

  Log Message:
  -----------
  [AArch64] Perform last active true vector combine

Test bit of lane EC-1 can use P register directly, eg:
Materialize : Idx = (add (mul vscale, NumEls), -1)
               i1 = extract_vector_elt t37, Constant:i64<Idx>
    ... into: "ptrue p, all" + PTEST

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D121180