[all-commits] [llvm/llvm-project] bd5f12: [RISCV] Add SimplifyDemandedBits support for FSR/F...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bd5f1247166a93bb5253db0116c474bc72e42505
      https://github.com/llvm/llvm-project/commit/bd5f1247166a93bb5253db0116c474bc72e42505
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-05 (Sat, 05 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbt-intrinsic.ll

  Log Message:
  -----------
  [RISCV] Add SimplifyDemandedBits support for FSR/FSL/FSRW/FSLW.