[all-commits] [llvm/llvm-project] 90c233: [AArch64][x86] add tests for bitwise logic + shift...

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 90c2330c15ffb8f5c3db86089f935e5a1bb9273a
      https://github.com/llvm/llvm-project/commit/90c2330c15ffb8f5c3db86089f935e5a1bb9273a
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-03-05 (Sat, 05 Mar 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/logic-shift.ll
    M llvm/test/CodeGen/X86/logic-shift.ll

  Log Message:
  -----------
  [AArch64][x86] add tests for bitwise logic + shifts; NFC

Copy tests from ecf606cb4329ae and replace 'or' with 'xor' / 'and'.
This provides coverage for an enhancement of D120516 / acb96ffd149d


  Commit: f4b53972ced23adbc5e6ef64ffd1c34f0f8f223f
      https://github.com/llvm/llvm-project/commit/f4b53972ced23adbc5e6ef64ffd1c34f0f8f223f
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-03-05 (Sat, 05 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/logic-shift.ll
    M llvm/test/CodeGen/X86/logic-shift.ll

  Log Message:
  -----------
  [SDAG] fold bitwise logic with shifted operands

This extends acb96ffd149d to 'and' and 'xor' opcodes.

Copying from that message:

LOGIC (LOGIC (SH X0, Y), Z), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z

https://alive2.llvm.org/ce/z/QmR9rR

This is a reassociation + factoring fold. The common shift operation is moved
after a bitwise logic op on 2 input operands.
We get simpler cases of these patterns in IR, but I suspect we would miss all
of these exact tests in IR too. We also handle the simpler form of this plus
several other folds in DAGCombiner::hoistLogicOpWithSameOpcodeHands().


Compare: https://github.com/llvm/llvm-project/compare/219a2eb4d48f...f4b53972ced2