[all-commits] [llvm/llvm-project] 65d532: [RISCV] More correctly ignore Zfinx register class...

[Shao-Ce SUN via All-commits]

  Branch: refs/heads/release/14.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 65d53279b1fddeae4bd455d588ea7527aed50bb9
      https://github.com/llvm/llvm-project/commit/65d53279b1fddeae4bd455d588ea7527aed50bb9
  Author: Shao-Ce SUN <shaoce at nj.iscas.ac.cn>
  Date:   2022-03-03 (Thu, 03 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
    M llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
    M llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll
    R llvm/test/CodeGen/RISCV/zfinx-types.ll

  Log Message:
  -----------
  [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint.

Until Zfinx is supported in CodeGen we need to convert all Zfinx
register classes to GPR.

Remove the zfinx-types.ll test which didn't test anything meaningful
since -mattr=zfinx isn't implemented completely in llc.

Follow up to D93298.

(cherry picked from commit 6cb42cd6669785f3b611106e1b6b38bbe65733a9)