[all-commits] [llvm/llvm-project] 324c0a: [SelectionDAG][RISCV] Emit a canonical sign bit te...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 324c0a72061e8337a62f9af1ffc5bf6f59b8340c
      https://github.com/llvm/llvm-project/commit/324c0a72061e8337a62f9af1ffc5bf6f59b8340c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/RISCV/iabs.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV] Emit a canonical sign bit test from ExpandIntRes_ABS.

Instead of emitting 0 > Hi, emit Hi < 0. If Hi needs to be expanded again
this will allow the special case for sign bit tests in ExpandIntOp_SETCC
to trigger.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D120761