[all-commits] [llvm/llvm-project] ac93f9: [LegalizeTypes][VP] Add splitting and widening sup...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac93f95861268c058d3f3bffd447a594a793c6b3
      https://github.com/llvm/llvm-project/commit/ac93f95861268c058d3f3bffd447a594a793c6b3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll

  Log Message:
  -----------
  [LegalizeTypes][VP] Add splitting and widening support for VP_FNEG.

Differential Revision: https://reviews.llvm.org/D120785


  Commit: a1f8349d770f7fc84e6109e6b398c42707506fd9
      https://github.com/llvm/llvm-project/commit/a1f8349d770f7fc84e6109e6b398c42707506fd9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-02 (Wed, 02 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll

  Log Message:
  -----------
  [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

This miscompile was introduced in D119527.

This was a special pattern for rotate+bswap on RV32. It doesn't
work for RV64 since the rotate needs to be half the bitwidth. The
equivalent pattern for RV64 is ROTR ((GREV x, 56), 32) so match
that instead.

This could be generalized further as noted in the new FIXME.

Reviewed By: Chenbing.Zheng

Differential Revision: https://reviews.llvm.org/D120686


Compare: https://github.com/llvm/llvm-project/compare/bf6477ebebf8...a1f8349d770f