[all-commits] [llvm/llvm-project] b9d6e8: [RISCV] Lower VECTOR_SPLICE to RVV instructions.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b9d6e8c44150cf03261f41c445839fa5505fb280
      https://github.com/llvm/llvm-project/commit/b9d6e8c44150cf03261f41c445839fa5505fb280
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-01 (Tue, 01 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    A llvm/test/CodeGen/RISCV/rvv/vector-splice.ll

  Log Message:
  -----------
  [RISCV] Lower VECTOR_SPLICE to RVV instructions.

This lowers VECTOR_SPLICE of scalable vectors to a slidedown follow by a slideup.
Fixed vectors are encouraged to use shufflevector instruction. The equivalent patch
for fixed vectors is D119039.

I've used a tail agnostic slidedown and limited the VL to only the
elements that will not be overwritten by the slideup. The slideup
uses VLMax for its VL. It unfortunately uses tail undisturbed policy
but it isn't required as there is no tail. We just need the merge
operand to carry the bits for the lower portion of the result.

Care was taken to ensure that either the slideup or slidedown will
be able to use a .vi instruction when the immediate is small. Which
one uses the immediate depends on the sign of the immediate.

Reviewed By: frasercrmck, ABataev

Differential Revision: https://reviews.llvm.org/D119303