[all-commits] [llvm/llvm-project] 57aaab: [NVPTX] Fix nvvm.match.sync*.i64 intrinsics return...

[chbessonova via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 57aaab3b17f02a0904b823278035afe555f6f99a
      https://github.com/llvm/llvm-project/commit/57aaab3b17f02a0904b823278035afe555f6f99a
  Author: Kristina Bessonova <kbessonova at accesssoftek.com>
  Date:   2022-03-01 (Tue, 01 Mar 2022)

  Changed paths:
    M clang/include/clang/Basic/BuiltinsNVPTX.def
    M clang/lib/Headers/__clang_cuda_intrinsics.h
    M clang/test/CodeGen/builtins-nvptx-ptx60.cu
    M llvm/include/llvm/IR/IntrinsicsNVVM.td
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    M llvm/test/CodeGen/NVPTX/match.ll

  Log Message:
  -----------
  [NVPTX] Fix nvvm.match.sync*.i64 intrinsics return type (i64 -> i32)

NVVM IR specification defines them with i32 return type:

  declare i32 @llvm.nvvm.match.any.sync.i64(i32 %membermask, i64 %value)
  declare {i32, i1} @llvm.nvvm.match.all.sync.i64(i32 %membermask, i64 %value)
  ...
  The i32 return value is a 32-bit mask where bit position in mask corresponds
  to thread’s laneid.

as well as PTX ISA:

  9.7.12.8. Parallel Synchronization and Communication Instructions: match.sync

  match.any.sync.type  d, a, membermask;
  match.all.sync.type  d[|p], a, membermask;
  ...
  Destination d is a 32-bit mask where bit position in mask corresponds
  to thread’s laneid.

Additionally, ptxas doesn't accept intructions, produced by NVPTX backend.
After this patch, it compiles with no issues.

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D120499