[all-commits] [llvm/llvm-project] cf80ef: [RISCV] Change GPRMemAtomic to GPRMemZeroOffset fo...

[eric-xtang1008 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf80ef1393979634526777a4b296fc2f0da6846a
      https://github.com/llvm/llvm-project/commit/cf80ef1393979634526777a4b296fc2f0da6846a
  Author: Eric Tang <eric.tang at starfivetech.com>
  Date:   2022-02-28 (Mon, 28 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td

  Log Message:
  -----------
  [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage

    Not only some AMO instructions but also other instructions need to
    process (${gpr}) or 0(${gpr}), where the 0 is be silently ignored.

    This patch does some changes for general usage.

Signed-off-by: Eric Tang <eric.tang at starfivetech.com>

Differential Revision: https://reviews.llvm.org/D120017


  Commit: 386c5be92a861f6aae95667e9ede2c573af84089
      https://github.com/llvm/llvm-project/commit/386c5be92a861f6aae95667e9ede2c573af84089
  Author: eric.tang <eric.tang at starfivetech.com>
  Date:   2022-02-28 (Mon, 28 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/MC/RISCV/priv-invalid.s
    M llvm/test/MC/RISCV/priv-valid.s
    M llvm/test/MC/RISCV/rvi-aliases-valid.s

  Log Message:
  -----------
  [RISCV] Support Sinval extension and hypervisor memory management fence instructions

    According to Privileged spec version-20211203

    Add Supervisor Memory-Management Instructions:
        - SINVAL.VMA, SFENCE.W.INVAL, SFENCE.INVAL.IR
    Add Hypervisor Memory-Management Instructions:
        - HFENCE.VVMA, HFENCE.GVMA, HINVAL.VVMA, HINVAL.GVMA

Signed-off-by: eric.tang <eric.tang at starfivetech.com>

Differential Revision: https://reviews.llvm.org/D117654


  Commit: b496a172e406479b129dd807960e602fe9babe57
      https://github.com/llvm/llvm-project/commit/b496a172e406479b129dd807960e602fe9babe57
  Author: eric.tang <eric.tang at starfivetech.com>
  Date:   2022-02-28 (Mon, 28 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    A llvm/test/MC/RISCV/priv-aliases-valid.s
    M llvm/test/MC/RISCV/priv-invalid.s
    A llvm/test/MC/RISCV/priv-rv64-invalid.s
    A llvm/test/MC/RISCV/priv-rv64-valid.s
    M llvm/test/MC/RISCV/priv-valid.s

  Log Message:
  -----------
  [RISCV] Support hypervisor extention instructions

    According to privileged spec version-20211203

    Add the following hypervisor instructions:
        - HLV.B HLV.BU
        - HLV.H HLV.HU HLVX.HU
        - HLV.W HLV.WU HLVX.WU
        - HLV.D
        - HSV.B HSV.H HSV.W HSV.D

Signed-off-by: eric.tang <eric.tang at starfivetech.com>

Differential Revision: https://reviews.llvm.org/D117733


Compare: https://github.com/llvm/llvm-project/compare/f467aa1b6477...b496a172e406