[all-commits] [llvm/llvm-project] 7ab78f: [SVE] Refactor complex immediate pattern used by C...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ab78f34cd3d90fda2c96ecdcca758617477c9ba
      https://github.com/llvm/llvm-project/commit/7ab78f34cd3d90fda2c96ecdcca758617477c9ba
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2022-02-25 (Fri, 25 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll

  Log Message:
  -----------
  [SVE] Refactor complex immediate pattern used by CPY/DUP.

SelectSVE8BitLslImm didn't account for constant values that have a
larger bit width than the result vector's element type.  This only
seems to affect a single corner case when lowering fixed length
vectors but the code itself is also not consistent with how other
related complex patterns are implemented so I've taken the
opportunity to refactor the code.

Differential Revision: https://reviews.llvm.org/D120440


  Commit: e109ce91b8b47fc34fb1301d89b1b8c04b27616b
      https://github.com/llvm/llvm-project/commit/e109ce91b8b47fc34fb1301d89b1b8c04b27616b
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2022-02-25 (Fri, 25 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

  Log Message:
  -----------
  [NFC][SVE] Refactor SelectSVEAddSubImm to match SelectSVECpyDupImm.

They're equivalent other than one is signed and the other unsigned.


Compare: https://github.com/llvm/llvm-project/compare/96918f2af67f...e109ce91b8b4