[all-commits] [llvm/llvm-project] a975ca: [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a975ca97c32f6a696c504a2341d856161663329d
      https://github.com/llvm/llvm-project/commit/a975ca97c32f6a696c504a2341d856161663329d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-24 (Thu, 24 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll

  Log Message:
  -----------
  [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).

Add a new ISD opcode to represent the sign extending behavior of
vmv.x.h. Keep the previous anyext opcode to allow the existing
(fmv_x_anyexth (fmv_h_x X)) combine to keep working without needing
to generate a sign extend.

For fmv.x.w we are able to match the sext_inreg in an isel pattern,
but a 16-bit sext_inreg is lowered to a shift pair before isel. This
seemed like a larger match than we should do in isel.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118974