[all-commits] [llvm/llvm-project] 440c4b: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssemb...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 440c4b705ad1d494a183b53cd65f21a481726157
      https://github.com/llvm/llvm-project/commit/440c4b705ad1d494a183b53cd65f21a481726157
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-20 (Sun, 20 Feb 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
    M llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
    M llvm/test/CodeGen/RISCV/rv32zbb.ll
    M llvm/test/CodeGen/RISCV/rv64zbb.ll
    M llvm/test/CodeGen/Thumb/iabs.ll
    M llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll
    M llvm/test/CodeGen/Thumb2/abs.ll
    M llvm/test/CodeGen/WebAssembly/PR41149.ll
    M llvm/test/CodeGen/X86/abs.ll
    M llvm/test/CodeGen/X86/combine-abs.ll
    M llvm/test/CodeGen/X86/iabs.ll
    M llvm/test/CodeGen/X86/neg-abs.ll
    M llvm/test/CodeGen/X86/viabs.ll
    M llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/basic.ll.expected

  Log Message:
  -----------
  [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).

Previous we used sra (X, size(X)-1); xor (add (X, Y), Y).

By placing sub at the end, we allow RISCV to combine sign_extend_inreg
with it to form subw.

Some X86 tests for Z - abs(X) seem to have improved as well.

Other targets look to be a wash.

I had to modify ARM's abs matching code to match from sub instead of
xor. Maybe instead ISD::ABS should be made legal. I'll try that in
parallel to this patch.

This is an alternative to D119099 which was focused on RISCV only.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D119171