[all-commits] [llvm/llvm-project] acc08a: Add "REQUIRES: asserts" to test misched-predicate-...

[dyung via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: acc08a2f1bd35a6046bffd7030bf3990ddd595c7
      https://github.com/llvm/llvm-project/commit/acc08a2f1bd35a6046bffd7030bf3990ddd595c7
  Author: Douglas Yung <douglas.yung at sony.com>
  Date:   2022-02-18 (Fri, 18 Feb 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir

  Log Message:
  -----------
  Add "REQUIRES: asserts" to test misched-predicate-virtreg.mir which uses "-debug-only".