[all-commits] [llvm/llvm-project] ca7831: [RISCV] Add the policy operand for nomask vector M...

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ca783124073f8db0900a38edd2647662484be09a
      https://github.com/llvm/llvm-project/commit/ca783124073f8db0900a38edd2647662484be09a
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2022-02-17 (Thu, 17 Feb 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
    M clang/utils/TableGen/RISCVVEmitter.cpp
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
    A llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

  Log Message:
  -----------
  [RISCV] Add the policy operand for nomask vector Multiply-Add IR intrinsics.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.

The nomask vector Multiply-Add need a policy operand
because merge value could not be undef.

Reviewed By: monkchiang

Differential Revision: https://reviews.llvm.org/D119727