[all-commits] [llvm/llvm-project] 954fe4: [RISCV] Fix incorrect MemOperand copy converting s...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 954fe404ab7f5dab917fe7987f68a3095ba10413
      https://github.com/llvm/llvm-project/commit/954fe404ab7f5dab917fe7987f68a3095ba10413
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-17 (Thu, 17 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

  Log Message:
  -----------
  [RISCV] Fix incorrect MemOperand copy converting splat+load to vlse.

Due to an incorrect copy/paste from load intrinsic handling we
checked if the splat node was a MemSDNode which of course it isn't.

Instead get the MemOperand from the LoadSDNode for the source of
the splat.

This enables LICM to see the load is loop invariant and hoist it
out of the loop.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D120014