[all-commits] [llvm/llvm-project] 2f2dcb: [AArch64][SVE] Invert VSelect operand order and co...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f2dcb4fb134a7e06d99ef62ca512c8307187207
      https://github.com/llvm/llvm-project/commit/2f2dcb4fb134a7e06d99ef62ca512c8307187207
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2022-02-17 (Thu, 17 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
    M llvm/test/CodeGen/AArch64/sve-select.ll

  Log Message:
  -----------
  [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations

   (vselect (setcc ( condcode) (_) (_)) (a)          (op (a) (b)))
=> (vselect (setcc (!condcode) (_) (_)) (op (a) (b)) (a))

As a follow up to D117689, invert the operand order and condition
in order to fold vselects into predicated instructions.

Differential Revision: https://reviews.llvm.org/D119424