[all-commits] [llvm/llvm-project] eeb775: [RISCV] Add the passthru operand for vmv.vv/vmv.vx...

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eeb7754f6853626c8ac1cb6b1436c1a3599ea182
      https://github.com/llvm/llvm-project/commit/eeb7754f6853626c8ac1cb6b1436c1a3599ea182
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2022-02-17 (Thu, 17 Feb 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

  Log Message:
  -----------
  [RISCV] Add the passthru operand for vmv.vv/vmv.vx/vfmv.vf IR intrinsics.

Add the passthru operand for
VMV_V_X_VL, VFMV_V_F_VL and SPLAT_VECTOR_SPLIT_I64_VL also.

The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D119688