[all-commits] [llvm/llvm-project] 6457f4: [DAGCombiner] Extend ISD::ABDS/U combine to handle...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6457f42bde82fd9a514434c946b9d3fbe92a8619
      https://github.com/llvm/llvm-project/commit/6457f42bde82fd9a514434c946b9d3fbe92a8619
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2022-02-17 (Thu, 17 Feb 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/neon-abd.ll
    M llvm/test/CodeGen/AArch64/sve-abd.ll
    M llvm/test/CodeGen/Thumb2/mve-vabdus.ll

  Log Message:
  -----------
  [DAGCombiner] Extend ISD::ABDS/U combine to handle more cases.

The current ABD combine doesn't quite work for SVE because only a
single scalable vector per scalar integer type is legal (e.g. for
i32, <vscale x 4 x i32> is the only legal scalable vector type).

This patch extends the combine to also trigger for the cases when
operand extension must be retained.

Differential Revision: https://reviews.llvm.org/D115739