[all-commits] [llvm/llvm-project] f3809b: [AArch64][SchedModels] Handle virtual registers in...

[Pavel Kosov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3809b20f2d97d0abdcdc5628c7093758aefc530
      https://github.com/llvm/llvm-project/commit/f3809b20f2d97d0abdcdc5628c7093758aefc530
  Author: Pavel Kosov <kosov.pavel at huawei.com>
  Date:   2022-02-17 (Thu, 17 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
    M llvm/lib/Target/AArch64/AArch64SchedPredicates.td
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
    M llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
    A llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir

  Log Message:
  -----------
  [AArch64][SchedModels] Handle virtual registers in FP/NEON predicates

Current implementation of Check[HSDQ]Form predicates doesn’t handle virtual registers and therefore isn’t useful for pre-RA scheduling. Patch fixes this implementing two function predicates: CheckQForm for checking that instruction writes 128-bit NEON register and CheckFpOrNEON which checks that instruction writes FP register (any width). The latter supersedes Check[HSD]Form predicates which are not used individually.

OS Laboratory. Huawei Russian Research Institute. Saint-Petersburg

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D114642


  Commit: 37fa99eda0f5e6d5b15f6bb726d3bcbeeed30c50
      https://github.com/llvm/llvm-project/commit/37fa99eda0f5e6d5b15f6bb726d3bcbeeed30c50
  Author: Pavel Kosov <kosov.pavel at huawei.com>
  Date:   2022-02-17 (Thu, 17 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA55.td
    M llvm/test/Analysis/CostModel/AArch64/vector-select.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll
    M llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
    M llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
    M llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
    M llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
    M llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
    M llvm/test/CodeGen/AArch64/arm64-vhadd.ll
    M llvm/test/CodeGen/AArch64/cmp-select-sign.ll
    M llvm/test/CodeGen/AArch64/dag-numsignbits.ll
    M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
    M llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
    M llvm/test/CodeGen/AArch64/expand-vector-rot.ll
    M llvm/test/CodeGen/AArch64/f16-instructions.ll
    M llvm/test/CodeGen/AArch64/fcopysign.ll
    M llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
    M llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
    M llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
    M llvm/test/CodeGen/AArch64/minmax-of-minmax.ll
    M llvm/test/CodeGen/AArch64/minmax.ll
    M llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
    M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/sat-add.ll
    M llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
    M llvm/test/CodeGen/AArch64/signbit-shift.ll
    M llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
    M llvm/test/CodeGen/AArch64/sinksplat.ll
    M llvm/test/CodeGen/AArch64/sitofp-fixed-legal.ll
    M llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
    M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll
    M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll
    M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
    M llvm/test/CodeGen/AArch64/vec_cttz.ll
    M llvm/test/CodeGen/AArch64/vec_uaddo.ll
    M llvm/test/CodeGen/AArch64/vec_umulo.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
    M llvm/test/CodeGen/AArch64/vector-fcopysign.ll
    M llvm/test/CodeGen/AArch64/vselect-constants.ll
    M llvm/test/tools/llvm-mca/AArch64/Cortex/A55-neon-instructions.s

  Log Message:
  -----------
  [SchedModels][CortexA55] Add ASIMD integer instructions

Depends on D114642

Original review https://reviews.llvm.org/D112201

OS Laboratory. Huawei Russian Research Institute. Saint-Petersburg

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D117003


Compare: https://github.com/llvm/llvm-project/compare/5065076698cf...37fa99eda0f5