[all-commits] [llvm/llvm-project] 3884cb: AMDGPU: Always reserve VGPR for AGPR copies on gfx908

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3884cb92359f68390816344f5e9bb40d78e492a5
      https://github.com/llvm/llvm-project/commit/3884cb92359f68390816344f5e9bb40d78e492a5
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    A llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
    M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll

  Log Message:
  -----------
  AMDGPU: Always reserve VGPR for AGPR copies on gfx908

Just because there aren't AGPRs in the original program doesn't mean
the register allocator can't choose to use them (unless we were to
forcibly reserve all AGPRs if there weren't any uses). This happens in
high pressure situations and introduces copies to avoid spills.

In this test, the allocator ends up introducing a copy from SGPR to
AGPR which requires an intermediate VGPR. I don't believe it would
introduce a copy from AGPR to AGPR in this situation, since it would
be trying to use an intermediate with a different class.

Theoretically this is also broken on gfx90a, but I have been unable to
come up with a testcase.