[all-commits] [llvm/llvm-project] 1daa66: [SelectionDAG] Add SPLAT_VECTOR to SelectionDAG::i...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1daa66d3fda96a7c6b670e05b9240a03fb8bd8a7
      https://github.com/llvm/llvm-project/commit/1daa66d3fda96a7c6b670e05b9240a03fb8bd8a7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/RISCV/rvv/combine-splats.ll

  Log Message:
  -----------
  [SelectionDAG] Add SPLAT_VECTOR to SelectionDAG::isConstantFPBuildVectorOrConstantFP.

Matches what is done for the int version.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D119793


  Commit: cfbbcc544c39b008bce5612148797d0f63bd26c7
      https://github.com/llvm/llvm-project/commit/cfbbcc544c39b008bce5612148797d0f63bd26c7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/alu64.ll
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/shift-masked-shamt.ll
    M llvm/test/CodeGen/RISCV/shifts.ll

  Log Message:
  -----------
  [RISCV] Improve lowering of SHL_PARTS/SRL_PARTS/SRA_PARTS.

Part of the shift lowering creates a (sub XLEN-1, ShAmt). When this
value is used we know that ShAmt is [0..XLEN-1]. Since XLEN is a power
of 2 we can replace the sub with an xor. This allows us to use XORI
instead of LI+SUB.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D119411


Compare: https://github.com/llvm/llvm-project/compare/f150d295da1e...cfbbcc544c39