[all-commits] [llvm/llvm-project] 064b2a: [DAGCombiner][AArch64] Enhance to fold CSNEG into ...

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 064b2a6dc6c947ebf9363a3ec917b84719e8941e
      https://github.com/llvm/llvm-project/commit/064b2a6dc6c947ebf9363a3ec917b84719e8941e
  Author: zhongyunde <zhongyunde at huawei.com>
  Date:   2022-02-16 (Wed, 16 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-isel-csinc-type.ll
    M llvm/test/CodeGen/AArch64/aarch64-isel-csinc.ll

  Log Message:
  -----------
  [DAGCombiner][AArch64] Enhance to fold CSNEG into CSINC instruction

Perform the scalar expression combine in the form of:
  CSNEG(1, c, cc) + b  =>  cc  ? b+1 : b-c => CSINC(b-c, b, !cc)
  CSNEG(c, -1, cc) + b =>  cc  ? b+c : b+1 => CSINC(b+c, b, cc)

Fix https://github.com/llvm/llvm-project/issues/53071

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D119105