[all-commits] [llvm/llvm-project] e72fe6: [DAGCombiner] Use getShiftAmountConstant in DAGCom...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e72fe654b72349d93b86a3dae28fc5bcce970f85
      https://github.com/llvm/llvm-project/commit/e72fe654b72349d93b86a3dae28fc5bcce970f85
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-13 (Sun, 13 Feb 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  Log Message:
  -----------
  [DAGCombiner] Use getShiftAmountConstant in DAGCombiner::foldSelectOfConstants.

This enables fshl to be matched earlier on X86

  %6 = lshr i32 %3, 1
  %7 = select i1 %4, i32 -2147483648, i32 0
  %8 = or i32 %6, %7

X86 uses i8 for shift amounts. SelectionDAGBuilder creates the
ISD::SRL with an i8 shift type. DAGCombiner turns the select into
an ISD::SHL. Prior to this patch it would use i32 for the shift
amount. fshl matching failed because the shift amounts have different
types. LegalizeDAG fixes the ISD::SHL shift amount to i8. This
allowed fshl matching to succeed.

With this patch, the ISD::SHL will be created with an i8 shift
amount. This allows the fshl to match immediately.

No test case beause we still end up with a fshl either way.