[all-commits] [llvm/llvm-project] 478c23: [RISCV] Fix incorrect extend type in vwmulsu combine.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 478c237e21b2c3a83e46f26fcbeb3876682f9b14
      https://github.com/llvm/llvm-project/commit/478c237e21b2c3a83e46f26fcbeb3876682f9b14
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-12 (Sat, 12 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulsu.ll

  Log Message:
  -----------
  [RISCV] Fix incorrect extend type in vwmulsu combine.

While matching widening multiply, if we matched an extend from i8->i32,
i16->i64 or i8->i64, we need to reintroduce a narrower extend. If we're
matching a vwmulsu we need to use a sext for op0 and a zext for op1.

This bug exists in LLVM 14 and will need to be backported.

Differential Revision: https://reviews.llvm.org/D119618