[all-commits] [llvm/llvm-project] a4ed0c: [X86] combineAndnp - if an input has a zero (after...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a4ed0c2f03e113aff988e21cf3cd75cabe0aaa0d
      https://github.com/llvm/llvm-project/commit/a4ed0c2f03e113aff988e21cf3cd75cabe0aaa0d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-02-12 (Sat, 12 Feb 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/avx512-insert-extract.ll
    M llvm/test/CodeGen/X86/combine-udiv.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll

  Log Message:
  -----------
  [X86] combineAndnp - if an input has a zero (after inversion for Op0) in a vector element, then we don't demand that bit/element in the other input

Similar to what we already perform in combineAnd