[all-commits] [llvm/llvm-project] af45d0: [AArch64] Adds SUBS and ADDS instructions to the M...

[Micah Weston via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af45d0fd94b21620b61c8c4900b81486fd85aeb7
      https://github.com/llvm/llvm-project/commit/af45d0fd94b21620b61c8c4900b81486fd85aeb7
  Author: Micah Weston <micahsweston at gmail.com>
  Date:   2022-02-12 (Sat, 12 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/test/CodeGen/AArch64/addsub.ll
    M llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll

  Log Message:
  -----------
  [AArch64] Adds SUBS and ADDS instructions to the MIPeepholeOpt.

Implements ADDS/SUBS 24-bit immediate optimization using the
MIPeepholeOpt pass. This follows the pattern:

Optimize ([adds|subs] r, imm) -> ([ADDS|SUBS] ([ADD|SUB] r, #imm0, lsl #12), #imm1),
if imm == (imm0<<12)+imm1. and both imm0 and imm1 are non-zero 12-bit unsigned
integers.

Optimize ([adds|subs] r, imm) -> ([SUBS|ADDS] ([SUB|ADD] r, #imm0, lsl #12), #imm1),
if imm == -(imm0<<12)-imm1, and both imm0 and imm1 are non-zero 12-bit unsigned
integers.

The SplitAndOpcFunc type had to change the return type to an Opcode pair so that
the first add/sub is the regular instruction and the second is the flag setting
instruction. This required updating the code in the AND case.

Testing:

I ran a two stage bootstrap with this code.
Using the second stage compiler, I verified that the negation of an ADDS to SUBS
or vice versa is a valid optimization. Example V == -0x111111.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D118663