[all-commits] [llvm/llvm-project] d224be: [RISCV] Add the policy operand for some masked RVV...

[Zakk Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d224be3b999afb7c4daa9c0ca807dea8123a7593
      https://github.com/llvm/llvm-project/commit/d224be3b999afb7c4daa9c0ca807dea8123a7593
  Author: Zakk Chen <zakk.chen at sifive.com>
  Date:   2022-02-11 (Fri, 11 Feb 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
    M clang/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vfmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll
    M llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslidedown-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vslideup-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll

  Log Message:
  -----------
  [RISCV] Add the policy operand for some masked RVV ternary IR intrinsics.

Masked reduction intrinsics are specical cases which don't need to have policy
operand. The mask only affects which elements are read. It doesn't effect the
destination register.
The reduction intrinsics have a dedicated destination operand. If it
is undef, we use tail agnostic. If it not undef we use tail
undisturbed.

Co-Authored-by: Craig Topper <craig.topper at sifive.com>

Differential Revision: https://reviews.llvm.org/D117681