[all-commits] [llvm/llvm-project] 02e0d5: [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02e0d50eb1e42eec9b236d9ce45f507ac69d9327
      https://github.com/llvm/llvm-project/commit/02e0d50eb1e42eec9b236d9ce45f507ac69d9327
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2022-02-10 (Thu, 10 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-limit-duplane.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-optimize-ptrue.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
    M llvm/test/CodeGen/AArch64/sve-vscale-attr.ll

  Log Message:
  -----------
  [SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.

These nodes provide an indirection that is not necessary because
SVE has unpredicated add/sub instructions and there's no downside
to using them for partial register operations. In fact, the test
changes show that unifying how fixed-length and scalable vector
add/sub are lowered enables better use of existing isel patterns.

Differential Revision: https://reviews.llvm.org/D119355