[all-commits] [llvm/llvm-project] d88a14: [AMDGPU] Missed sign/zero extend patterns for dive...

[alex-t via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d88a146f2bc1422997f98ac9c8030af32e744433
      https://github.com/llvm/llvm-project/commit/d88a146f2bc1422997f98ac9c8030af32e744433
  Author: alex-t <alexander.timofeev at amd.com>
  Date:   2022-02-10 (Thu, 10 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    A llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
    M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
    M llvm/test/CodeGen/AMDGPU/sext-divergence-driven-isel.ll
    A llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll

  Log Message:
  -----------
  [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection

This change includes tablegen patterns that were missed by https://reviews.llvm.org/D110950 and https://reviews.llvm.org/D76230

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D119302