[all-commits] [llvm/llvm-project] 8b5849: [AArch64] Improve codegen for get.active.lane.mask...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8b58494cea784f413a27418823ae2f97fde96371
      https://github.com/llvm/llvm-project/commit/8b58494cea784f413a27418823ae2f97fde96371
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-02-10 (Thu, 10 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/active_lane_mask.ll

  Log Message:
  -----------
  [AArch64] Improve codegen for get.active.lane.mask when SVE is available

When lowering the get.active.lane.mask intrinsic with a fixed-width
predicate vector result, we can actually make use of the SVE whilelo
instruction when SVE is enabled. We do this by carefully choosing
a sensible VT for the whilelo instruction, then promoting it to an
integer vector, i.e. nxv16i1 -> nx16i8. We can then extract a v16i8
subvector and truncate back to the original return type, i.e. v16i1.
This leads to a significant improvement in code quality.

Differential Revision: https://reviews.llvm.org/D116664