[all-commits] [llvm/llvm-project] c45c1b: [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask t...

Craig Topper via All-commits all-commits at lists.llvm.org
Wed Feb 9 12:37:07 PST 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c45c1b130b5cdb16426f5f7758a8518ea449ff69
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-09 (Wed, 09 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll
    M llvm/test/CodeGen/RISCV/shifts.ll

  Log Message:
  [RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to replace sub from constant with neg.

If the shift amount is (sub C, X) where C is 0 modulo the size of
the shift, we can replace it with neg or negw.

Similar is is done for AArch64 and X86.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D119089

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