[all-commits] [llvm/llvm-project] 56d6cc: [X86] Update register RCL/RCR by 1 and immediate s...
Craig Topper via All-commits
all-commits at lists.llvm.org
Tue Feb 8 09:34:55 PST 2022
Author: Craig Topper <craig.topper at sifive.com>
Date: 2022-02-08 (Tue, 08 Feb 2022)
[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs
Most Intel CPU scheduler files lumped the immediate and 1 instructions
together, but uops.info shows they are quite different.
For the most part the by 1 instructions were pretty accurate to the uops.info
data except the latency was 3 instead of 2 as uops.info indicates.
The by immediate instructions need 7 or 8 uops and have higher latency.
It looks like the 8-bit by immediate instructions may need even more
uops, but I just lumped them with the 16/32/64.
Noticed while checking out PR53648. So mostly I cared about the by 1
Reviewed By: RKSimon, pengfei
Differential Revision: https://reviews.llvm.org/D119217
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