[all-commits] [llvm/llvm-project] 56d6cc: [X86] Update register RCL/RCR by 1 and immediate s...

Craig Topper via All-commits all-commits at lists.llvm.org
Tue Feb 8 09:34:55 PST 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 56d6ccd4cb4aac4c23ac50ae51f9cebb4ea1ad29
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-08 (Tue, 08 Feb 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86SchedBroadwell.td
    M llvm/lib/Target/X86/X86SchedHaswell.td
    M llvm/lib/Target/X86/X86SchedIceLake.td
    M llvm/lib/Target/X86/X86SchedSandyBridge.td
    M llvm/lib/Target/X86/X86SchedSkylakeClient.td
    M llvm/lib/Target/X86/X86SchedSkylakeServer.td
    M llvm/test/tools/llvm-mca/X86/Barcelona/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/Broadwell/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/Generic/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/IceLakeServer/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/SkylakeClient/resources-x86_64.s
    M llvm/test/tools/llvm-mca/X86/SkylakeServer/resources-x86_64.s

  Log Message:
  [X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs

Most Intel CPU scheduler files lumped the immediate and 1 instructions
together, but uops.info shows they are quite different.

For the most part the by 1 instructions were pretty accurate to the uops.info
data except the latency was 3 instead of 2 as uops.info indicates.

The by immediate instructions need 7 or 8 uops and have higher latency.

It looks like the 8-bit by immediate instructions may need even more
uops, but I just lumped them with the 16/32/64.

Noticed while checking out PR53648. So mostly I cared about the by 1

Reviewed By: RKSimon, pengfei

Differential Revision: https://reviews.llvm.org/D119217

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