[all-commits] [llvm/llvm-project] eabae1: [AArch64][CodeGen] Always use SVE (when enabled) t...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eabae1b0175691d1f979299b22a25ed4474864a0
      https://github.com/llvm/llvm-project/commit/eabae1b0175691d1f979299b22a25ed4474864a0
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-02-08 (Tue, 08 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll

  Log Message:
  -----------
  [AArch64][CodeGen] Always use SVE (when enabled) to lower 64-bit vector multiplies

This patch adds custom lowering support for ISD::MUL with v1i64 and v2i64
types when SVE is enabled, regardless of the minimum SVE vector length. We
do this because NEON simply does not have 64-bit vector multiplies, so we
want to take advantage of these instructions in SVE.

I've updated the 128-bit min SVE vector bits tests here:

  CodeGen/AArch64/sve-fixed-length-int-arith.ll
  CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  CodeGen/AArch64/sve-fixed-length-int-rem.ll

Differential Revision: https://reviews.llvm.org/D118802