[all-commits] [llvm/llvm-project] c35ccd: [DAGCombiner][RISCV] Allow rotates by non-constant...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c35ccd2ac852bec22c5eafb65bf0e9adb1451df0
      https://github.com/llvm/llvm-project/commit/c35ccd2ac852bec22c5eafb65bf0e9adb1451df0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-06 (Sun, 06 Feb 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll

  Log Message:
  -----------
  [DAGCombiner][RISCV] Allow rotates by non-constant to be matched for i32 on riscv64 with Zbb.

rv64izbb has a RORW/ROLW instructions that operate on the lower
32-bits of a 64-bit value and sign extend bit 31 of the result.

DAGCombiner won't match rotate idioms because the i32 type isn't Legal
on riscv64.

This patch teaches DAGCombiner to allow it if the type is going to
be promoted and the target has Custom type legalization for ISD::ROTL
or ISD::ROTR. I've restricted this to scalar types. It doesn't appear
any in tree targets other than riscv64 have custom type legalization
for rotates.

If this patch isn't acceptable, I guess I can match SRLW, SLLW, and OR
after type legalization, but I'd like to avoid that if possible.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D119062